High-level Analysis for Reconfiguration of a Fault Tolerant Mesh-based NoC Architecture Using Transaction Level Modeling

In this paper we propose a fault-tolerant architecture for mesh-based network on chips to recover from permanent faults in switches. We add a number of spare links between processing elements and their neighboring switches and some logic redundancy to network elements. Also online fault detection and correction strategies are presented for this architecture. We model and simulate the communication behavior of the proposed architecture and recovery methods using TLM. Fast simulation speed of TLM as a high-level description language helps us in easy design exploration of our faulttolerant architecture and finding the most efficient architecture for it. Later in the design process, it is possible to refine this TLM model to lower abstraction levels and synthesize it to an actual hardware. Index Terms — Fault-tolerant Architecture, Networks on Chip, Transaction Level Modeling